NAND not booting on a new OMAP3 board? check this list out
The following check list was compiled based on a discussion here
a) Did you check if the device id of the device is in TRM under
supported devices? -> ROM Code should support this device if it should ever boot..
b) Did you read your CTRL_STATUS register and verify the SYSBOOT boot sequence in TRM -> is NAND in the sequence and nothing else preventing it from being hit?
c) what is the status of your EMU0-1 JTAG pins are they both high or in tristate condition during OMAP boot? -> the wrong setting would prevent boot sequence from being executed
d) is it on CS0? -> well OMAP boots out of CS0
e) Do you have an 8 bit or a 16 bit NAND? is your config file in
x-loader, u-boot handling this correctly? -> accessing wrong width is not very helpful.. ;)
f) Did you sign x-loader.bin.ift with signGP.c? Try this in x-loader
directory: grep _start System.map|cut -d' ' -f1|xargs signGP x-load.bin -> x-loader loads up at the address we tell it to, few variants of x-loaders seem to use different base addresses.. just to be sure..sign the x-loader correctly
g) Finally did you use nandecc hw for flashing x-loader.bin.ift? - well.. that is the only ECC formatting that OMAP ROM Code understands..
h) what is the result of nand dump 0? the OOB area? - this verifies the ECC organization
i) you could in theory write a very small piece of assembly to shut down watchdog timer, and basically loop for ever -> flash this instead of x-loader then once the board boots up, connect with JTAG and see if your infinite loop is running in SRAM.. if so, you have your flashing correct, but mebbe x-loader is goofing up somewhere.. -> this is just my fav way of debug..
a) Did you check if the device id of the device is in TRM under
supported devices? -> ROM Code should support this device if it should ever boot..
b) Did you read your CTRL_STATUS register and verify the SYSBOOT boot sequence in TRM -> is NAND in the sequence and nothing else preventing it from being hit?
c) what is the status of your EMU0-1 JTAG pins are they both high or in tristate condition during OMAP boot? -> the wrong setting would prevent boot sequence from being executed
d) is it on CS0? -> well OMAP boots out of CS0
e) Do you have an 8 bit or a 16 bit NAND? is your config file in
x-loader, u-boot handling this correctly? -> accessing wrong width is not very helpful.. ;)
f) Did you sign x-loader.bin.ift with signGP.c? Try this in x-loader
directory: grep _start System.map|cut -d' ' -f1|xargs signGP x-load.bin -> x-loader loads up at the address we tell it to, few variants of x-loaders seem to use different base addresses.. just to be sure..sign the x-loader correctly
g) Finally did you use nandecc hw for flashing x-loader.bin.ift? - well.. that is the only ECC formatting that OMAP ROM Code understands..
h) what is the result of nand dump 0? the OOB area? - this verifies the ECC organization
i) you could in theory write a very small piece of assembly to shut down watchdog timer, and basically loop for ever -> flash this instead of x-loader then once the board boots up, connect with JTAG and see if your infinite loop is running in SRAM.. if so, you have your flashing correct, but mebbe x-loader is goofing up somewhere.. -> this is just my fav way of debug..
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