is nand ecc correction logic sane enough?

for some time now, I have gone with the belief that the nand ecc imlementation such as this which I helped write good enough for nand devices, but Vimal Singh pointed me to these two articles:
http://lists.infradead.org/pipermail/linux-mtd/2008-August/022611.html
http://lists.infradead.org/pipermail/linux-mtd/2008-August/022613.html

Essentially:
If we do just old_ecc^new_ecc to detect/correct ecc errors - the logic handles the case of bit flip error at 63rd bit(as e.g.) faultily. I was completely unaware of this weakness of the algo.. thanks Vimal for pointing me here..

I have plans of setting up a bit of code to verify this (essentially hack up the current drivers by overriding the read path ;) ).. will post if I can proove(I suspect this would be the case) this is the case with gpmc..